1. Technical Field
Various embodiments of the present invention relate to a semiconductor circuit and, more particularly, to a phase correction circuit, a data alignment circuit and method of aligning data using the is same.
2. Related Art
A semiconductor circuit, such as a memory, performs a write operation for aligning and recording data provided from outside according to a data strobe signal DQS.
A tDQSS is a specification value that defines a time difference between a clock signal and a data strobe signal. Even though a memory controller outputs two signals by setting a tDQSS to ‘0’, the tDQSS between the clock signal and the data strobe signal inputted to a memory can have a value other than ‘0’ due to a “skew” occurring at a board level.
Since the tDQSS is defined on the basis of a clock signal period (tCK), it becomes more difficult to satisfy the tDQSS specification as the operation speed (e.g., frequency of the clock signal) of the memory increases. In this regard, a memory such as a DDR3 provides a function called “write leveling” to satisfy the tDQSS specification in an input pad. At this time, the tDQSS specification needs to satisfy ±0.25*tCK.
The write leveling is performed as follows. The memory controller outputs the clock signal and the data strobe signal to the memory. The memory samples the clock signal at the rising edge of the data strobe signal. The memory feeds the sampling results back to the memory controller through a DQ pad. The memory controller adjusts the delay of the data strobe signal until the value of the sampling result becomes ‘1’ and then completes the write leveling.
While the memory is affected by a variation in PVT (process, voltage or temperature) in a normal operation, the write leveling is performed only in the initial step before the memory performs the normal operation. Therefore, there is no method capable of compensating for the skew of the clock signal and the data strobe signal, which occurs in the normal operation of the memory.